An in-depth look at prior art in fast round-robin arbiter circuits

Arbiters are found where shared resources exist such as busses, switching fabrics, processing elements. Round-robin is a fair arbitration method, where requestors get near-equal shares of a common resource or service. Round-robin arbitration (RRA) finds use in network switches/routers and processor boards/systems as well as many other applications that have concurrency. Today's electronic systems require arbiters with hundreds of ports (e.g., switching fabrics with virtual I/O queues) and clock speeds near the limits of even the latest microelectronics fabrication processes/libraries. Achieving high clock speeds in the presence of large number of ports is only possible with highly parallel arbiter architectures. This paper presents an in-depth literature survey of previous work on this problem. It looks at RRA work in the literature in a bigger context, then defines the typical RRA problem (RRA_typical), and specifically investigates work on fast architectures that solve the RRA_typical problem. There are five such works that are really competitive. This report takes a very in-depth look at these works. It explains each architecture and how/why it works from a unique perspective that cannot be found in the original publication of that architecture. It also proposes improvements to these architectures. We wrote generators for the improved versions of these architectures. We will share a summary of synthesis results in this report – although a detailed account of how these results were obtained and their analysis is the subject of another (upcoming) publicatio

A robotics summer camp for high school students: pipelines activities promoting careers in engineering fields

In this paper we discuss the lived-experiences and the career interests of 27 high school students who participated in a two-week Robotics summer camp in 2012. The summer camp was designed by a team of engineering faculty, graduate students, and undergraduates. It provided the high school students with the opportunity to play and work with the materials to design a robot, build it, test it, and re-design it. A secondary purpose of the camp was to help students determine their career choice in the engineering fields. The participating 27 students were selected according to (a) their content questionnaire scores administered to 145 students in 34 different locations (b) personal interest essays, and (c) phone interviews. At the camp, the students took (a) a computer programming course, (b) a basic electronics course, and (c) proteus, pic, and microC training sessions. The students in pairs designed, built, tested, and modified their robots through practical implementations. They were given a variety of design challenges in each practical implementation. In the camp, invited researchers presented about their research and interest in Robotics and showed interdisciplinary perspectives of Robotics activities in the field (e.g., cardiovascular surgery). Also the students attended other extracurricular activities (e.g., a field trip to Ford Company). Study data were collected through interviews, field notes, and observations. The analysis of the qualitative data indicated that the camp increased the students’ interest in engineering and helped them determine specific engineering fields that they wish to study in their academic career. Our observations revealed that the participating students engaged in activities with a community of engineers and gained first hand and original engineering design experience. We organized the study findings along with three dimensions: (a) Robotics summer camp as alternative to traditional learning environment in schools, (b) robotics activities as a means to nurture student interest in engineering fields and (c) robotics summer camp as venue for the students to determine specific engineering fields. Our study findings suggest offering outreach programs in practical engineering work to high school students.publisher versio

Experiences on the road from EDA developer to designer to educator

Due to copyright restrictions, the access to the full text of this article is only available via subscription.This paper will coin some concepts that came to being as an engineer once made a journey from EDA developer of a behavioral synthesis tool to RTL designer and then on to academia. The EDA developer in disguise of logic designer found comfort in writing Perl scripts writing out Verilog. He defended this unorthodox practice with buzzwords of "semi-automation", "RTL generators", and "manual behavioral synthesis" (MBS). Then, the design engineer in disguise of a professor taught his students what he did best and called it "hardware design patterns". The paper includes examples of where these concepts (especially MBS) were used, along with references to others' uses of semi-automation

Cost-benefit approach to degradation of electrolytic capacitors

Due to copyright restrictions, the access to the full text of this article is only available via subscription.Aluminum electrolytic capacitors are widely used as a filter or bulky capacitor after rectification stages of switching power supplies (SMPS). Fly-back, forward, and resonant converter topologies, which are widely used in consumer electronics products, computer power supplies, and various kind of adapters, require electrolytic capacitors (EL. CAP.) in primary stage and secondary stages for rectification to smooth non-DC current. Electrolytic capacitors must be used because of size and capacitance, unit price, and to withstand voltage. Overall reliability of an SMPS mainly depends on electrolytic capacitors used, because they have extremely short lifetime compared to other active and passive components. Failure modes of electrolytic capacitors are either catastrophic failures or degradation failures. Catastrophic failures generally occur because of fabrication processes. Degradation failures are seen during gradual aging of electrolytic capacitors. During degradation, electrochemical aging occurs between Al2O3 foils and electrolytic solvent, and this creates hydrogen gas inside cap. Degradation process also increases equivalent series resistance (ESR) and decreases capacitance. This degradation is mainly dependent on heat and is somewhat predictable, because main degradation agent is a heat-triggered accelerated electrochemical reaction. Previous works in the literature disclose the obvious fact that this degradation process due to heat can be modeled by a modified Arrhenius Equation, and therefore, it is an exponential curve [1][2]. All commercially available capacitors have their base rated life duration specified in their datasheets, given in hours, such as 1000 hrs, 2000 hrs, 5000 hrs, etc. Those values are measured according to the international standard IEC60384 (or Japanese equivalent JIS-C-5101) and are called “base life”. In an SMPS design, the real usage life of a capacitor is calculated based on the temperature that i- is used at. The acceleration factor is calculated with a modified approximation formula and multiplied with base life to calculate the predicted life. Low grade capacitors cause many capacitor plague issues and products of different manufacturers show completely different lifetime performance even their specifications and base lifetime are the same. In this paper, low and medium-grade capacitors from three different manufacturers and high-grade capacitors from two different Japanese manufacturers are selected and tested at their maximum allowable temperature limits, allowable max voltage and ripple current. Total of 100 samples are used during tests from each different manufacturer. Degradation of each capacitor brand, required life and unit cost are evaluated, and a cost/life optimization has been formulized between low-grade capacitors and high-grade capacitors. In the literature, there are a number of notable works carried out on degradation analysis of electrolytic capacitors; however, there is no comparative analysis of low cost capacitors used in consumer devices. The derived novel method is a useful tool to choose electrolytic capacitors for consumer products that use high voltage (≤450 V) on the primary side and low voltage (≤65 V) on the secondary side of SMPS. This cost-benefit approximation for capacitor selection process gives good opportunity to design engineers to do the selection based on reliability and overall cost. Results show that the optimized capacitor is not the cheapest, most expensive, or most reliable one; optimal capacitor is a modest Chinese “CAP. B”. It is the most desirable solution that minimizes overall cost inside the warranty duration

Fast parallel prefix logic circuits for n2n round-robin arbitration

Due to copyright restrictions, the access to the full text of this article is only available via subscription.An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period

Welcome from the general chairs

Due to copyright restrictions, the access to the full text of this article is only available via subscription

Fast parallel prefix logic circuits for n2n round-robin arbitration

Due to copyright restrictions, the access to the full text of this article is only available via subscription.An n2n round-robin arbiter (RRA) searches its n inputs for a 1, starting from the highest-priority input. It picks the first 1 and outputs its index in one-hot encoding. RRA aims to be fair to its inputs and maintains fairness by simply rotating the input priorities, i.e., the last arbitrated input becomes the lowest-priority input. Arbiters are used to multiplex the usage of shared resources among requestors as well as in dispatch logic where the purpose is load balancing among multiple resources. Today, arbiters have hundreds of ports and usually need to run at very high clock speeds. This article presents a new gate-level RRA circuit called Thermo Coded-Parallel Prefix Arbiter (TC-PPA) that scales to any number of requestors. It uses parallel prefix network topologies (borrowed from fast carry lookahead adders) to generate a thermometer-coded pointer, thus greatly reducing critical path. Code generators were written not only for TC-PPA but also for the 5 highly competitive circuits in the literature (9 including their variants), and a rich set of timing/area results were obtained using a standard-cell based logic synthesis flow with a novel iterative strategy based on binary search. Synthesis runs include results with wire-load and without. Results show that for 54 or more ports (except 256) TC-PPA offers the best timing (lowest latency) as well as competitive area. Contributions also include transaction-level simulations that show when pipelining is used to boost clock rate, latency and input FIFO sizes are adversely affected, and hence pipelining cannot be indiscriminately exploited to trim clock period

Fast two-pick n2n round-robin arbiter circuit

Due to copyright restrictions, the access to the full text of this article is only available via subscription.A regular (one-pick) round-robin arbiter circuit picks one active requester (if any) out of n requesters. A two-pick round-robin arbiter selects up to two requesters. An n2n two-pick round-robin arbiter indicates the picked requests with (at most) two-hot n-bit output. A round-robin arbiter is fair to its requesters and does this by repeatedly moving its highest priority pointer to the position immediately next to the second requester picked. Presented is the circuit architecture and VLSI implementation of a new scalable two-pick round-robin arbiter with low latency, which is compared with previous work based on logic synthesis results

HM-net: A regression network for object center detection and tracking on wide area motion imagery

Wide Area Motion Imagery (WAMI) yields high resolution images with a large number of extremely small objects. Target objects have large spatial displacements throughout consecutive frames. This nature of WAMI images makes object tracking and detection challenging. In this paper, we present our deep neural network-based combined object detection and tracking model, namely, Heat Map Network (HM-Net). HM-Net is significantly faster than state-of-the-art frame differencing and background subtraction-based methods, without compromising detection and tracking performances. HM-Net follows object center-based joint detection and tracking paradigm. Simple heat map-based predictions support unlimited number of simultaneous detections. The proposed method uses two consecutive frames and the object detection heat map obtained from the previous frame as input, which helps HM-Net monitor spatio-temporal changes between frames and keep track of previously predicted objects. Although reuse of prior object detection heat map acts as a vital feedback-based memory element, it can lead to unintended surge of false positive detections. To increase robustness of the method against false positives and to eliminate low confidence detections, HM-Net employs novel feedback filters and advanced data augmentations. HM-Net outperforms state-of-the-art WAMI moving object detection and tracking methods on WPAFB dataset with its 96.2% F1 and 94.4% mAP detection scores, while achieving 61.8 % mAP tracking score on the same dataset. This performance corresponds to an improvement of 2.1% for F1, 6.1% for mAP scores on detection, and 9.5% for mAP score on tracking over state-of-the-art